About The Position
Participating in the analysis, architecture and design of a multi standard (3GPP) SDR, as part of the company’s next generation chipset development
Architecture and Design
· Analyzing standard, marketing and product requirements to create PHY / LMAC requirements.
· Define the architecture in terms of: required algorithm performance, required resources (memory, latency, etc.), develop data path flows, top level SDR architecture.
· Lead features in an end-to-end approach (from product/standard definition through implementation up to defining criteria for compliance)
· Analyze system performance bottlenecks, suggest improvements as needed. Identify limitations. Perform initial study and modeling, as needed.
· Write detailed specification documents for implementation of Algo/DSP/FW teams.
Standard activity and innovations
- Monitor on-going standard activity, identify topics with potential relevance to existing/new products
- Evaluate new or missing features from our current design
- Contribute as necessary to standardization activity, on a per demand basis
Cross-teams interaction and support
- Communicate and update with product team
- Support system integration for new features
Interact and contribute to brainstorming with DSP/Algo/SW teams
B.Sc in EE/Communication systems engineering from a university, focusing on signal processing for communication
10 years of experience or M.Sc in EE with at least 5 years of experience in:
Modem/Phy architecture and/or system engineering (can be combined with Algo and/or DSP)
Able to transform standardization papers into Phy requirements and design
Able to guide VLSI, Algo and DSP development from technical aspects
Team player, fast learner.